A. Technical Field
The invention generally relates to a process for manufacturing memory cells. More particularly, the invention relates to a self-aligned trench capacitor capping process for high density DRAM cells.
B. Background of the Invention
FIG. 1 shows a trench capacitor for use in a 256 Mbit DRAM. The trench capacitor includes substrate 100 with trench 101. Filling trench 101, is polycrystalline silicon 102. Near the top of trench 101 is collar 103. A side of collar 103 is open to diffusion region 114, which is connected to diffusion region 113 forming the drain region of MOS transistor 114. MOS transistor 114 also includes gate 115, gate oxide 105, and source diffusion region 112. Word line 109 connects gate 115 a shallow trench isolation (STI) region 107 isolates trench 101 from other trenches. The top of polycrystalline silicon 102 is bounded by silicon nitride layer 106 to contain the shallow trench isolation 107. The silicon nitride layer 106 is also referred to as an STI liner. Oxide 104 acts as a buffer between polycrystalline silicon 102 and silicon nitride layer 106. On top of shallow trench isolation 107, word line 110 passes by word line 114 without affecting the operation of the capacitor formed in trench 102.
Total STI height may be almost 300 nm (250 nm under surface and 50 nm above the surface).
To create silicon nitride layer 106, the layer is deposited then etched back using conventional process steps (not shown for simplicity). However, when etching back, the difference between the etching rates of silicon 100, oxide 104-105, silicon nitride (STI liner layer) 106, and shallow trench fill 107 result in a non-planar surface for the device during processing. FIG. 1B shows in greater detail the non-planar resultant structure. FIG. 1B is taken along line II of Figure IA. As shown in FIG. 1B, the beginning of the shallow trench isolation region is a recessed polycrystalline silicon trench 201. Lining the sides of trench 201 is oxide 202. Silicon nitride 203 (also referred to as a trench top capping film) is formed on top of oxide 202. Shallow trench isolation fill 204 fills the remaining area bounded by trench liner 203. As described above, processing the wafer after deposition results in a non-planar surface. At least one reason is that the different etching rates of the STI 204, oxide 202, and trench liner 203 result in an edge of trench liner 203 rising above the surrounding recessed material (oxide 202 and STI fill 204). The resulting non-planar surface of the wafer reduces yield as lithographic techniques cannot adequately focus on the surface of the wafer due to its non-planar features. Further, the oxidation layer 104 consumes the top surface of the polycrystalline silicon node 102 of the trench capacitor. It is difficult to control STI edge shape uniformly due to the rising edge of trench liner 203. This shape impacts the threshold voltage of the transistor.
In response to the problems stemming from the conventional capping process described above, an improved process for capping a trench capacitor is disclosed. The capping process of the invention includes deposition of a silicon nitride pad during the formation of the trench capacitor. After deposition of the pad, the pad is patterned to provide access to the underlying trench. The top service is etched to recess the top surface of the trench below the surface of the surrounding top surface of the wafer. Next, the recessed top surface of the trench is deposited with the trench-capping silicon nitride. The side of the trench to be overlaid with a passing word line is subjected to a deep etch to provide for shallow trench isolation. The exposed surface of the trench is subjected to oxidation to form a buffer and the remaining cavity is filled with STI fill. The surface of the wafer is etched back or subjected to chemical-mechanical polishing to planarize the surface of the wafer. The silicon nitride pad is then removed to expose the surface of the wafer. Finally, a gate oxide is grown or deposited and a gate electrode formed.
In an alternative embodiment of the invention, the surface of the trench may be oxidized prior to deposition of the trench cap. This oxidation provides a buffer between the silicon nitride trench cap and the polycrystalline silicon of the trench.
These and other novel advantages, details, embodiments, features and objects of the present invention will be apparent to those skilled in the art from following the detailed description of the invention, the attached claims and accompanying drawings, listed herein, which are useful in explaining the invention.